A 2.2GHz 7.6mW sub-sampling PLL with .126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 392-394

  Gao, Xiang ^a   Klumperink, Eric A M ^a   Bohsali, Mounir ^b   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349295873     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977473     Document Type: Conference Paper

References (7)

1. C. S. Vaucher, Architectures for RF Frequency Synthesizers, Kluwer, 2002.
2. X. Gao, et al., "Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops," IEEE Trans. Circuits and Systems-II, Accepted for publication.
3. J. A. Crawford, Frequency Synthesizer Design Handbook, Artech House, 1994.
4. R. C.H. van de Beek, C. S. Vaucher, D. M.W. Leenaerts, et al., "A 2.5 to 10 GHz clock Multiplier Unit with 0.22ps RMS Jitter in a 0.18μm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 178-179, Feb., 2003.
5. R. Gu, A. Yee, Y. Xie, and W. Lee, "A 6.25GHz 1V LC-PLL in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 594-595, Feb., 2006.
6. C. Hsu, M.Z. Straayer, and M.H. Perrott, "A Low-Noise, Wide-BW 3.6GHz Digital Δ∑ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation," ISSCC Dig. Tech. Papers, pp. 340-341, Feb., 2008.
7. D. Banerjee, PLL Performance, Simulation, and Design, 4th Edition, National Semiconductor, 2006. Accessed on Dec. 4, 2008 http://www.national.com/ analog/timing/pll-designbook.