A 6-μW chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 9, 2010, Pages 1896-1905

  Guo, Jianping ^a   Leung, Ka Nang ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Capacitor less; low dropout regulator (LDO); nano scale technology; transient response

Indexed keywords

AREA EFFICIENT; CAPACITIVE LOADS; CAPACITOR-LESS; CLASS-AB OPERATIONS; CMOS TECHNOLOGY; CURRENT CHANGE; FAST TRANSIENTS; FULL-LOAD; HIGH STABILITY; LINE REGULATION; LOAD CAPABILITY; LOAD REGULATIONS; LOOP GAINS; LOW-DROPOUT REGULATORS; MAXIMUM OVERSHOOT; MILLER CAPACITORS; NANO SCALE; OFF-CHIP CAPACITORS; PARASITIC CAPACITANCE; POWER CONSUMPTION; POWER TRANSISTORS; RECOVERY TIME; SPIKE DETECTION; TRANSIENT RESPONSE; VOLTAGE SPIKES;

CAPACITORS; CMOS INTEGRATED CIRCUITS; EQUIVALENT CIRCUITS; NANOSTRUCTURED MATERIALS; POWER ELECTRONICS; TECHNOLOGY; TRANSIENT ANALYSIS;

ELECTRIC CURRENT REGULATORS;

EID: 77956193261     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2053859     Document Type: Conference Paper

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