A low-dropout regulator for SoC with Q-reduction

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 3, 2007, Pages 658-664

  Lau, Sai Kit ^a,b,c   Mok, Philip K T ^a,b   Leung, Ka Nang ^a,b,d  

^a IEEE   (Hong Kong)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^c Pericom Technology Incorporated   (Hong Kong)

^d CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Low dropout regulator; Power management; Q reduction

Indexed keywords

LOW-DROPOUT REGULATORS; POWER MANAGEMENT; Q-REDUCTION; REGULATOR-CIRCUIT IMPLEMENTATION;

CAPACITANCE; OPTIMIZATION; Q FACTOR MEASUREMENT; STANDARDS; VOLTAGE CONTROL;

CMOS INTEGRATED CIRCUITS;

EID: 33847697655     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.891496     Document Type: Article

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