An efficient verification method for a class of multi-phase sequential circuits

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2000, Pages 510-515

  Boyer, François R ^a   Aboulhamid, El Mostapha ^a   Savaria, Yvon ^b  

^a UNIVERSITÉ DE MONTRÉAL   (Canada)

^b ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK PHASIS; COMBINATIONAL CIRCUITS; COMBINATIONAL OPTIMIZATION; DESIGN PROCESS; PRACTICAL METHOD; RETIMING; TOOLS AND METHODS; VERIFICATION METHOD; VERIFICATION TOOLS;

HAND TOOLS; OPTIMIZATION; SCHEDULING ALGORITHMS; SEQUENTIAL CIRCUITS;

EQUIVALENCE CLASSES;

EID: 77956023701     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.911590     Document Type: Conference Paper

References (9)

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8. Ranjan, R. K., Singhal, V., Somenzi, F., and Brayton, R. K.: Using Combinational Verification for Sequential Circuits. Proceeding of Design Automation and Test in Europe, 1999.
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