Optimal design of synchronous circuits using software pipelining techniques

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 62-67

  Boyer, Francois R ^a   Aboulhamid, El Mostapha ^a   Savaria, Y ^a   Bennour, I E ^a  

^a UNIVERSITÉ DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; CRITICAL PATH ANALYSIS; SHIFT REGISTERS;

SOFTWARE PIPELINING; SYNCHRONOUS CIRCUITS;

PIPELINE PROCESSING SYSTEMS;

EID: 0032295843     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)