Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 16-24

  Bischoff, Gabriel P ^a   Brace, Karl S ^a   Jain, Samir ^a   Razdan, Rahul ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; FORMAL LOGIC; INTERFACES (COMPUTER); SCHEMATIC DIAGRAMS; SEQUENTIAL MACHINES;

BUS INTERFACE UNIT (BIU); FORMAL VERIFICATION; REGISTER TRANSFER LEVEL (RTL);

MICROPROCESSOR CHIPS;

EID: 0031339083     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)