Analysis of layout density in FinFET standard cells and impact of fin technology

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 3204-3207

  Alioto, Massimo ^a,b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIN HEIGHT; GATE LIBRARIES; GEOMETRIC CONSTRAINT; PHYSICAL LEVEL; STANDARD CELL;

ELECTRIC BATTERIES; FABRICS; FINS (HEAT EXCHANGE); FORCED CONVECTION; INTEGRATED CIRCUITS; LOGIC CIRCUITS; STANDARDS; SWITCHING CIRCUITS;

ELECTRIC NETWORK ANALYSIS;

EID: 77956008816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537930     Document Type: Conference Paper

References (13)

1. T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, F. Boeuf, "The end of CMOS scaling," IEEE Circuits & Devices Magazine, pp. 16-26, Jan.-Feb. 2005.
2. International Technology Roadmvap for Semiconductors. 2007 Edition.
3. M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk Technology," in print on IEEE Trans. on VLSI Systems, available at http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04383015
4. E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C.-T. Chuang, K. Bernstein, R. Puri, "Turning silicon on its edge," IEEE Circuits & Devices Magazine, pp. 20-31, Jan.-Feb. 2004.
5. J. P. Collinge (Ed.), FinFETs and Other Multi-Gate Transistors, Springer, 2008.
6. K. G. Anil, K. Henson, S. Biesemans, and N. Collaert, "Layout density analysis of FinFET," in Proceeding of ESSDERC 2003, Sept 2003, pp. 139-142.
7. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm FinFET: PFET," in Tech. Digest IEDM 1999, Washington, DC, pp. 67-70.
8. Y.-K. Choi, T.-J. King, C. Hu, "A Spacer Patterning Technology for Nanoscale CMOS," IEEE Trans. on Electron Devices, vol. 49, no. 3, pp. 436-441, March 2002.
9. B. Degroote, et Al., "Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density," Microelectronic Engineering, vol. 84, no. 4, pp. 609-618, April 2007.
10. Y.-K. Choi, T.-J. King, C. Hu, "Nanoscale CMOS Spacer FinFET for the Terabit Era," IEEE Electron Device Letters, vol. 23, no. 1, pp. 436-441, Jan. 2002.
11. T. Ludwig, I. Aller, V. Gemhoefer, J. Keinelt, E. Nowak, R. V. Joshi, A. Mueller and S. Tomaschko "FinFET Technology for Future Microprocessors, " in Proc. of SOI Conference 2003, pp. 33-34, 2003.
12. T.-J. King, FinFETs for Nanoscale CMOS Digital Integrated Circuits, presentation available at http://www.leb.eei.unierlangen. de/winterakademie/ 2008/courses/course3-material/alternativ eMOS/King-FinFET.pdf.
13. N. Collaert, et al. "Tall triple-gate device with TiN/HfO2 gate stack," in Proc. of Symposium on VLSI Technology, pp. 108-109, Leuven (Belgium), 2005.