Minimizing energy consumption of a chip multiprocessor through simultaneous core consolidation and DVFS

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 49-52

  Ghasemazar, Mohammad ^a   Pakbaznia, Ehsan ^a   Pedram, Massoud ^a  

^a University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSOR; CLOCK FREQUENCY; DYNAMIC POWER; ENERGY SAVING; MINIMIZING ENERGY; MINIMUM ENERGY; MULTI PROCESSOR SYSTEMS; NP-HARD PROBLEM; PROCESSOR CORES; SOLUTION APPROACH; SUPPLY VOLTAGES; TASK ASSIGNMENT; THREE-LEVEL; THROUGHPUT CONSTRAINTS; TOTAL ENERGY CONSUMPTION;

ENERGY UTILIZATION; MULTIPROCESSING SYSTEMS; OPTIMIZATION;

FABRICS;

EID: 77955988667     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537096     Document Type: Conference Paper

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