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Volumn 57, Issue 4 PART 1, 2010, Pages 1820-1826

Analysis of SET propagation in Flash-based FPGAs by means of electrical pulse injection

Author keywords

Characterization; flash based FPGAs; single event transients (SETs)

Indexed keywords

BASIC LOGIC; CIRCUIT LOGIC; COMBINATIONAL LOGIC; CRITICAL BEHAVIOR; EFFECTIVE ANALYSIS; ELECTRICAL PULSE; EXPERIMENTAL ANALYSIS; FLASH-BASED FPGAS; LOGIC PATH; LOGIC RESOURCES; PLACE AND ROUTE; SET PROPAGATION; SINGLE EVENT EFFECTS; SINGLE EVENT TRANSIENTS; SINGLE EVENT TRANSIENTS (SETS); TECHNOLOGY SCALING;

EID: 77955817641     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2010.2043686     Document Type: Conference Paper
Times cited : (32)

References (12)
  • 2
    • 58849108227 scopus 로고    scopus 로고
    • Configuration and routing effects on the SET propagation in flash-based FPGAs
    • Dec.
    • S. Rezgui, J. J. Wang, Y. Sun, B. Cronquist, and J. McCollum, "Configuration and routing effects on the SET propagation in flash-based FPGAs," IEEE Trans. Nucl. Sci., vol.55, no.6, pp. 3328-3335, Dec. 2008.
    • (2008) IEEE Trans. Nucl. Sci. , vol.55 , Issue.6 , pp. 3328-3335
    • Rezgui, S.1    Wang, J.J.2    Sun, Y.3    Cronquist, B.4    McCollum, J.5
  • 6
    • 58849108227 scopus 로고    scopus 로고
    • Configuration and routing effects on the SET propagation in flash-based FPGAs
    • Dec.
    • S. Rezgui, J. J. Wang, Y. Sun, B. Cronquist, and J. McCollum, "Configuration and routing effects on the SET propagation in flash-based FPGAs," IEEE Trans. Nucl. Sci., vol.55, no.6, pp. 3328-3335, Dec. 2008.
    • (2008) IEEE Trans. Nucl. Sci. , vol.55 , Issue.6 , pp. 3328-3335
    • Rezgui, S.1    Wang, J.J.2    Sun, Y.3    Cronquist, B.4    McCollum, J.5
  • 9
    • 67649845766 scopus 로고    scopus 로고
    • Measuring the effectiveness of symmetric and asymmetric transistor sizing for single event transient mitigation in CMOS 90 nm technologies
    • T. Assis, F. L. Kastensmidt, G. Wirth, and R. Reis, "Measuring the effectiveness of symmetric and asymmetric transistor sizing for single event transient mitigation in CMOS 90 nm technologies," in Proc. 10th Latin American Test Workshop, 2009, pp. 1-6.
    • (2009) Proc. 10th Latin American Test Workshop , pp. 1-6
    • Assis, T.1    Kastensmidt, F.L.2    Wirth, G.3    Reis, R.4
  • 10
    • 77955808529 scopus 로고    scopus 로고
    • ProAsic3 Flash Family FPGAs Datasheet
    • ProAsic3 Flash Family FPGAs Datasheet.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.