Simulation of junctionless Si nanowire transistors with 3 nm gate length

Applied Physics Letters

Volumn 97, Issue 6, 2010, Pages

  Ansari, Lida ^a   Feldman, Baruch ^a   Fagas, Giorgos ^a   Colinge, Jean Pierre ^a   Greer, James C ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LEVELS; DESIGN PHILOSOPHY; FIRST-PRINCIPLES; GATE LENGTH; LENGTH SCALE; PROOF OF CONCEPT; SI NANOWIRE; SI-BASED; SILICON NANOWIRES; THEORETICAL SIMULATION; WIRE DIAMETER;

NANOWIRES; TRANSISTORS;

SILICON;

EID: 77955756447     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3478012     Document Type: Article

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16. g =0 V but introducing a uniform energy shift to the NEGF Hamiltonian in the gated region. This neglects capacitance and screening in the oxide and SiNW but enables us to quantify the tunneling current through the channel.