Multi-port abstraction layer for FPGA intensive memory exploitation applications

Journal of Systems Architecture

Volumn 56, Issue 9, 2010, Pages 442-451

  Vanegas, M ^a,b   Tomasi, M ^a   Diaz J ^a   Ros, E ^a  

^a UNIVERSITY OF GRANADA   (Spain)

^b UNIVERSIDAD PONTIFICIA BOLIVARIANA   (Colombia)

Author keywords

FPGA; Hardware design; Memory control unit; Real time processing; Video processing

Indexed keywords

FPGA; HARDWARE DESIGN; MEMORY-CONTROL UNIT; REALTIME PROCESSING; VIDEO PROCESSING;

DESIGN; HARDWARE; ROUTERS; SCHEDULING; VIDEO SIGNAL PROCESSING;

ABSTRACTING;

EID: 77955658264     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2010.05.007     Document Type: Article

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