Performance evaluation of VHDL coding techniques for optimized implementation of IEEE 802.3 transmitter

IET Conference Publications

Volumn , Issue 535 CP, 2008, Pages 287-293

  Sutaone, M S ^a   Badwaik, S C ^b  

^a Department of Instrumentation & Control Engineering   (India)

^b PIMPRI CHINCHWAD COLLEGE OF ENGINEERING   (India)

Author keywords

Fan out Register balancing; Finite state machine; Linear feed back shift register; Media access control transmitter; Multiplexer extraction; Priority encoder extraction

Indexed keywords

FAN OUT REGISTER BALANCING; FINITE STATE MACHINE; LINEAR FEED BACK SHIFT REGISTER; MEDIA ACCESS CONTROL TRANSMITTER; MULTIPLEXER EXTRACTION; PRIORITY ENCODER EXTRACTION;

ACCESS CONTROL; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CONSTRAINED OPTIMIZATION; CONTOUR FOLLOWERS; FEEDBACK; MULTIPLEXING; MULTIPLEXING EQUIPMENT; OPTIMIZATION; SECURITY SYSTEMS; SHIFT REGISTERS; SPEED; TRANSMITTERS;

WIRELESS NETWORKS;

EID: 67449095126     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/cp:20080199     Document Type: Conference Paper

References (6)

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3. "IEEE computer society IEEE std 802.3™-2005" (revision of IEEE std 802.3-2002 including all approved Amendments)
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