Reliability modeling of lead-free solder joints in wafer-level chip scale packages

Journal of Electronic Packaging

Volumn 132, Issue 1, 2010, Pages 0110051-0110056

  Zhao, Jie Hua ^a   Gupta, Vikas ^a   Lohia, Alok ^a   Edwards, Darvin ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FINITE ELEMENT METHOD; LEAD-FREE SOLDERS; SOLDERED JOINTS; STRAIN ENERGY;

BOARD-LEVEL; CONSTITUTIVE LAW; CORRELATION PARAMETERS; FATIGUE LIFETIME; FINITE ELEMENT METHOD MODEL (FEM); LEAD-FREE SOLDER JOINT; POWER-LAW; RELIABILITY MODELLING; THERMO MECHANICAL FATIGUES (TMF); WAFER-LEVEL CHIP SCALE PACKAGES;

CREEP;

EID: 77955265278     PISSN: 10437398     EISSN: 15289044     Source Type: Journal    
DOI: 10.1115/1.4000754     Document Type: Article

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