SCOPUS 정보 검색 플랫폼

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 297-302

The advanced pattern designs with electrical test methodologies on through silicon via for CMOS image sensor

(10) Chung, Hsien a Ni, Ching Yu b Tu, Che Min a Chang, Yu Yao a Haung, Yao Te b Chen, Wei Ming b Lou, Bai Yao b Tseng, Kun Fu c Lee, Chih Yuan a Lwo, Ben Je a

a NATIONAL DEFENSE UNIVERSITY (Taiwan)

b Xintec Inc (Taiwan)

c CHIN MIN INSTITUTE OF TECHNOLOGY (Taiwan)

Author keywords

CMOS Image Sensor; Electrical Characterization; Through Silicon Via (TSV); Wafer Level Interconnection

Indexed keywords

3-D INTEGRATION; CMOS IMAGE SENSOR; ELECTRICAL CHARACTERIZATION; ELECTRICAL CONTINUITY; ELECTRICAL MEASUREMENT; ELECTRICAL TESTS; METAL LAYER; ON-WAFER; PATTERN DESIGNS; TEST PATTERN; THROUGH-SILICON-VIA; VIA RESISTANCE; WAFER LEVEL;

CONTACT RESISTANCE; DESIGN; DIGITAL CAMERAS; DIGITAL IMAGE STORAGE; IMAGE SENSORS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS;

ELECTRONICS PACKAGING;

EID: 77955207780 PISSN: 05695503 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ECTC.2010.5490958 Document Type: Conference Paper

Times cited : (13)

References (8)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.