Towards optimizing energy costs of algorithms for shared memory architectures

Annual ACM Symposium on Parallelism in Algorithms and Architectures

Volumn , Issue , 2010, Pages 157-165

  Korthikanti, Vijay Anand ^a   Agha, Gul ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Energy; Parallel algorithms; Performance; Shared memory architectures

Indexed keywords

COMPUTATION STEPS; ENERGY CONSUMPTION; MULTI-CORE PROCESSOR; OPTIMAL NUMBER; OPTIMIZING ENERGY; PERFORMANCE REQUIREMENTS; POWER CONSUMED; PROBLEM SIZE; SHARED MEMORIES; SHARED MEMORY ARCHITECTURE; SPECIFIC PROBLEMS;

OPTIMIZATION; PARALLEL ALGORITHMS; PARALLEL ARCHITECTURES;

ELECTRIC LOAD FORECASTING;

EID: 77954896487     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1810479.1810510     Document Type: Conference Paper

References (24)

1. http://www.greenpeace.org/raw/content/international/press/reports/ make-it-green-cloud-computing.pdf. Greenpeace International, 2010.
2. A. Aggarwal and S. Vitter, Jeffrey. The input/output complexity of sorting and related problems. Communications of ACM, 31(9):1116-1127, 1988.
3. L. Arge, M. T. Goodrich, M. J. Nelson, and N. Sitchinava. Fundamental parallel algorithms for private-cache chip multiprocessors. In SPAA, pages 197-206, 2008.
4. M. A. Bender, J. T. Fineman, S. Gilbert, and B. C. Kuszmaul. Concurrent cache-oblivious b-trees. In SPAA, pages 228-237, 2005.
5. B. D. Bingham and M. R. Greenstreet. Computation with energy-time trade-offs: Models, algorithms and lower-bounds. In ISPA, pages 143-152, 2008.
6. G. E. Blelloch, R. A. Chowdhury, P. B. Gibbons, V. Ramachandran, S. Chen, and M. Kozuch. Provably good multicore cache performance for divide-and-conquer algorithms. In SODA, pages 501-510, 2008.
7. A. Chandrakasan, S. Sheng, and R. Brodersen. Low-power cmos digital design. IEEE Journal of Solid-State Circuits, 27(4):473-484, 1992.
8. S. Cho and R. Melhem. Corollaries to Amdahl's Law for Energy. Computer Architecture Letters, 7(1):25-28, 2008.
9. M. Curtis-Maury, A. Shah, F. Blagojevic, D. Nikolopoulos, B. de Supinski, and M. Schulz. Prediction Models for Multi-dimensional Power-Performance Optimization on Many Cores. In International Conference on Parallel architectures and compilation techniques, pages 250-259, 2008.
10. R. Ge, X. Feng, and K. Cameron. Performance-Constrained Distributed DVS Scheduling for Scientific Applications on Power-Aware Clusters. In International Conference on Supercomputing. IEEE Computer Society Washington, DC, USA, 2005.
11. R. Gonzalez and M. A. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31:1277U″1284, 1995.
12. M. T. Goodrich. Communication-efficient parallel sorting. SIAM Journal of Computing, 29(2):416-432, 1999.
13. C. Isci, A. Buyuktosunoglu, C. Cher, P. Bose, and M. Martonosi. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. In International Symposium on Microarchitecture, volume 9, pages 347-358, 2006.
14. R. M. Karp and V. Ramachandran. Parallel algorithms for shared-memory machines. Handbook of Theoretical Computer Science (vol. A): Algorithms and Complexity, pages 869-941, 1990.
15. V. A. Korthikanti and G. Agha. Analysis of parallel algorithms for energy conservation in scalable multicore architectures. In ICPP, pages 212-219, 2009.
16. V. Kumar, A. Grama, A. Gupta, and G. Karypis. Introduction to Parallel Computing: Design and Analysis of Algorithms. Benjamin-Cummings Publishing Co., Inc. Redwood City, CA, USA, 1994.
17. R. E. Ladner and M. J. Fischer. Parallel prefix computation. ACM Journal, 27(4):831-838, 1980.
18. J. Li and J. Martinez. Power-Performance Considerations of Parallel Computing on Chip Multiprocessors. ACM Transactions on Architecture and Code Optimization, 2(4):1-25, 2005.
19. J. Li and J. Martinez. Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors. In International Symposium on High-Performance Computer Architecture, pages 77-87, 2006.
20. A. J. Martin. Towards an energy complexity of computation. Information Processing Letters, 39:181U″187, 2001.
21. M. P. Mills. The internet begins with coal. Green Earth Society, USA, 1999.
22. R. Murphy. On the effects of memory latency and bandwidth on supercomputer application performance. IEEE International Symposium on Workload Characterization, pages 35-43, Sept. 2007.
23. S. Park, W. Jiang, Y. Zhou, and S. Adve. Managing Energy-Performance Tradeoffs for Multithreaded Applications on Multiprocessor Architectures. In ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pages 169-180. ACM New York, NY, USA, 2007.
24. X. Wang and S. Ziavras. Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors. In International Symposium on Quality Electronic Design, pages 386-391, 2007.