Prediction models for multi-dimensional power-performance optimization on many cores

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2008, Pages 250-259

  Curtis Maury, Matthew ^a   Shah, Ankur ^a   Blagojevic, Filip ^a   Nikolopoulos, Dimitrios S ^a   De Supinski, Bronis R ^b   Schulz, Martin ^b  

^a State University   (United States)

^b LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

Author keywords

Management; Measurement; Performance

Indexed keywords

CONSTRAINED SYSTEMS; CORE SYSTEMS; DEVELOPED APPLICATIONS; DYNAMIC POWER CONSUMPTION; DYNAMIC VOLTAGE AND FREQUENCY SCALING; ENERGY SAVINGS; HEURISTIC SEARCHES; MANY CORES; MULTI-CORE SYSTEMS; ON-LINE PERFORMANCE; OPTIMAL SETTINGS; PERFORMANCE; PERFORMANCE IMPROVEMENTS; PERFORMANCE OPTIMIZATIONS; POWER SAVINGS; POWER-AWARE; PREDICTION MODELS; PROGRAMMING FRAMEWORKS; REAL SYSTEMS; RUN-TIME ADAPTATIONS; RUN-TIME LIBRARIES; RUN-TIME OPTIMIZATIONS; SOFTWARE TOOLS; SYNERGISTIC INTEGRATIONS;

CLUTCHES; CONCURRENCY CONTROL; DECODING; DISCRETE COSINE TRANSFORMS; KNOBS; MICROPROCESSOR CHIPS; OCCUPATIONAL RISKS; ONLINE SYSTEMS; OPTIMIZATION; PARALLEL ARCHITECTURES; PARALLEL PROGRAMMING;

COSINE TRANSFORMS;

EID: 63549125482     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1454115.1454151     Document Type: Conference Paper

References (29)

1. M. Azimi, N. Cherukuri, D. Jayashima, A. Kumar, P. Kundu, S. Park, I. Schoinas, and A. Vaidya. Integration Challenges and Tradeoffs for Tera-scale Architectures. Intel Technology Journal, August 2007.
2. S. Browne, J. Dongarra, N. Garner, K. London, and P. Mucci. A Scalable Cross-Platform Infrastructure for Application Performance Tuning Using Hardware Counters. In Proc. of Supercomputing'2000, November 2000.
3. E. V. Carrera, E. Pinheiro, and R. Bianchini. Conserving Disk Energy in Network Servers. In Proc. of the 17th International Conference on Supercomputing, June 2003.
4. K. Chakraborty, P. Wells, and G. Sohi. A Case for an Over-provisioned Multicore System: Energy Efficient Processing of Multithreaded Programs. Technical Report TR-1607, Department of Computer Sciences, University of Wisconsin-Madison, 2007.
5. M. Curtis-Maury, F. Blagojevic, C. D. Antonopoulos, and D. S. Nikolopoulos. Prediction-Based Power-Performance Adaptation of Multithreaded Scientific Codes. IEEE Transactions on Parallel and Distributed Systems. Accepted, to appear, 2008.
6. M. Curtis-Maury, J. Dzierwa, C. Antonopoulos, and D. Nikolopoulos. Online Power-Performance Adaptation of Multithreaded Programs using Hardware Event-Based Prediction. In Proc. of the International Conference on Supercomputing, June 2006.
7. B. Diniz, D. O. G. Neto, W Meira Jr., and R. Bianchini. Limiting the Power Consumption of Main Memory. In Proc. of the International Symposium on Computer Architectures, June 2007.
8. R. Ge, X. Feng, and K. W Cameron. Performance constrained Distributed DVS Scheduling for Scientific Applications on Power-aware Clusters. In Proc. of Supercomputing, November 2005.
9. C.-H. Hsu and W. Feng. A Power-Aware Run-Time System for High-Performance Computing. In Proc. of Supercomputing'05, November 2005.
10. C. Huang, O. Lawlor, and L. Kale. Adaptive MPI. In Proc. of the 16th International Workshop on Languages and Compilers for Parallel Computing LNCS 2948, 2003.
11. C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. In Proc. of the International Symposium on Microarchitecture, December 2006.
12. C. Isci and M. Martonosi. Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data. In Proc. of the Annual International Symposium on Microarchitecture, December 2003.
13. E. Joseph, A. Snell, C. G. Willard, S. Tichenor, D. Shaffer, and S. Conway. Council on Competitiveness Study of ISVs Serving the High Performance Computing Market. July 2005.
14. T.S. Karkhanis and J.E. Smith. A First-Order Superscalar Processor Model. In Proc. of the 31st International Symposium on Computer Architecture, June 2004.
15. S. Kumar, H. Raj, K. Schwan, and I. Ganev. Re-architecting VMMs for Multicore Systems: The Sidecore Approach. In Proc. of the 2007 Workshop on the Interaction between Operating Systems and Computer Architecture, June 2007.
16. B. C. Lee and D. M. Brooks. Accurate and Efficient Regression Modeling for Microarchitectural Performance and Power Prediction. In Proc. of the International Conference on Architectural Support for Programming Languages and Operating Systems, October 2006.
17. B. C. Lee, D. M. Brooks, B. R. de Supinski, M. Schulz, K. Singh, and S. A. McKee. Methods of Inference and Learning for Performance Modeling of Parallel Applications. In Proc. of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, November 2007.
18. J. Li and J. Martinez. Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multi-Processors. In Proc. of the International Symposium on High Performance Computer Architecture, February 2006.
19. Y. Li and B. C. Lee and D. Brooks and Z. Hu and K. Skadron. CMP Design Space Exploration Subject to Physical Constraints. In Proc. of the IEEE International Symposium on High Performance Computer Architecture, February 2006.
20. C. Liu, A. Sivasubramaniam, M. T. Kandemir, and M. J. Irwin. Exploiting Barriers to Optimize Power Consumption of CMPs. In Proc. of the 19th International Parallel and Distributed Processing Symposium, April 2005.
21. A. Merkel and F. Bellosa. Balancing Power Consumption in Multiprocessor Systems. In Proc. of EuroSys Conference, April 2006.
22. T. Moseley, J. Kim, D. Connors, and D. Grunwald. Methods for Modeling Resource Contention on Simultaneous Multithreaded Processors. In Proc. of the 2005 International Conference on Computer Design, October 2005.
23. V. Pallipadi and A. Starikovskiy. The Ondemand Governor. In Proc. of the Ottawa Linux Symposium, July 2006.
24. S. Park, W Jiang, Y Zhou, and S. V. Adve. Managing Energy-Performance Tradeoffs for Multithreaded Applications on Multiprocessor Architectures. In Proceedings of the 2007 ACM SIGMETRICS, June 2007.
25. R. Springer, D. K. Lowenthal, B. Rountree, and V. W Freeh. Minimizing Execution Time in MPI Programs on an Energy-Constrained, Power-Scalable Cluster. In Proc. of the Symposium on Principles and Practice of Parallel Programming, March 2006.
26. A. Varma, B. Ganesh, M. Sen, S. R. Choudhury, L. Srinivasan, and B. L. Jacob. A Control-Theoretic Approach to Dynamic Voltage Scheduling. In Proc. of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, October 2003.
27. A. Weissel and F. Bellosa. Process Cruise Control: Event-Driven Clock Scaling for Dynamic Power Management. In Proc. of the International Conference on Compilers, Architectures and Synthesis of Embedded Systems, October 2002.
28. Q. Wu, P. Juang, M. Martonosi, and D. W Clark. Formal Online Methods for Voltage/Frequency Control in Multiple Clock Domain Microprocessors. In Proc. of the International Conference on Architectural Support for Programming Languages and Operating Systems, 2004.
29. Q. Wu, M. Martonosi, D. Clark, V. Reddi, D. Connors, Y Wu, J. Lee, and D. Brooks. Dynamic Compiler-Driven Control for Microprocessor Energy and Performance. IEEE Micro, 26(1), 2006.