Provably good multicore cache performance for divide-and-conquer algorithms

Proceedings of the Annual ACM-SIAM Symposium on Discrete Algorithms

Volumn , Issue , 2008, Pages 501-510

  Blelloch, Guy E ^a   Chowdhury, Rezaul A ^b   Gibbons, Phillip B ^c   Ramachandran, Vijaya ^b   Chen, Shimin ^c   Kozuch, Michael ^c  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE COMPLEXITY; CACHE PERFORMANCE; MULTI CORE PROCESSORS; MULTI CORES; TIME COMPLEXITIES;

ALGORITHMS; SCHEDULING; SEQUENTIAL SWITCHING;

PARALLEL ALGORITHMS;

EID: 58449090994     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (30)

1. www.sun.com/processors/UltraSPARC-T1/, 2007.
2. www.tilera.com, 2007.
3. Intel shows off 80-core processor. www.news.com/2100-1006-3-6158181.html, 2007.
4. U. A. Acar, G. E. Blelloch, and R. D. Blumofe. The data locality of work stealing. Theory of Computing Systems, 35(3), 2002. Springer.
5. A. Aggarwal, B. Alpern, A. Chandra, and M. Snir. A model for hierarchical memory. In ACM STOC, 1987.
6. A. Aggarwal and J. S. Vitter. The input/output complexity of sorting and related problems. Communications of the ACM, 31(9), 1988.
7. S. Akl and N. Santoro. Optimal parallel merging and sorting without memory conflicts. IEEE Transactions on Computers, 36(11), 1987.
8. B. Alpern, L. Carter, E. Feig, and T. Selker. The uniform memory hierachy model of computation. Algorthmica, 12(2/3), 1994. Springer.
9. L. A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. Piranha: A scalable architecture based on single-chip multiprocessing. In ACM ISCA, 2000.
10. M. A. Bender, G. S. Brodal, R. Fagerberg, R. Jacob, and E. Vicari. Optimal sparse matrix dense vector multiplication in the I/O-model. In ACM SPAA, 2007.
11. M. A. Bender, J. T. Fineman, S. Gilbert, and B. C. Kuszmaul. Concurrent cache-oblivious B-trees. In ACM SPAA, 2005.
12. G. E. Blelloch and P. B. Gibbons. Effectively sharing a cache among threads. In ACM SPAA, 2004.
13. G. E. Blelloch, P. B. Gibbons, and Y. Matias. Provably efficient scheduling for languages with fine-grained parallelism. Journal of the ACM, 46(2), 1999.
14. G. E. Blelloch, P. B. Gibbons, Y. Matias, and G. J. Narlikar. Space-efficient scheduling of parallelism with synchronization variables. In ACM SPAA, 1997.
15. R. D. Blumofe, M. Frigo, C. F. Joerg, C. E. Leiserson, and K. H. Randall. An analysis of dag-consistent distributed shared-memory algorithms. In ACM SPAA, 1996.
16. R. Brent. The parallel evaluation of general arithmeticexpressions. Journal of the ACM, 21:201-206, 1974.
17. E. Chan, E. S. Qumtana-Orti, G. Quintana-Orti, and R. van de Geijn. Supennatrix out-of-order scheduling of matrix operations for SMP and multi-core architectures. In ACM SPAA, 2007.
18. S. Chen, P. B. Gibbons, M. Kozuch, V. Liaskovitis, A. Ailamaki, G. E. Blelloch, B. Falsafi, L. Fix, N. Hardavellas, T. C. Mowry, and C. Wilkerson. Scheduling threads for constructive cache sharing on CMPs. In ACM SPAA, 2007.
19. R. Chowdhury and V. Ramachandran. The cacheoblivious gaussian elimination paradigm: Theoretical framework, parallelization and experimental evaluation. In ACM SPAA, 2007.
20. A. Fedorova, M. Seltzer, C. Small, and D. Nussbaum. Performance of multithreaded chip multiprocessors and implications for operating system design. In USENIX Ann. Tech. Conf., 2005.
21. M. Frigo, C. E. Leiserson, H. Prokop, and S. Ramachandran. Cache-oblivious algorithms. In IEEE FOCS, 1999.
22. M. Frigo and V. Strumpen. The cache complexity of multithreaded cache oblivious algorithms. In ACM SPAA, 2006.
23. M. T. Goodrich, M. Nelson, and N. Sitchinava. Sorting in parallel external-memory multicores. Technical report, U.C. Irvine, 2007.
24. L. Hammond, B. A. Hubbert, M. Siu, M. K. Prabhu, M. Chen, and K. Olukotun. The Stanford Hydra CMP. IEEE Micro, 20(2), 2000.
25. L. Hammond, B. Nayfeh, and K. Olukotun. A singlechip multiprocessor. IEEE Computer, 30(9), 1997.
26. R. J. Lipton and R. E. Tarjan. A separator theorem for planar graphs. SIAM Journal on Applied Mathematics, 36(2), 1979.
27. G. J. Narlikar. Scheduling threads for low space requirement and good locality. Theory of Computing Systems, 35(2), 2002. Springer.
28. B. A. Nayfeh, L. Hammond, and K. Olukotun. Evaluation of design alternatives for a multiprocessor microprocessor. In ACM ISCA, 1996.
29. V. Strassen. Gaussian elimination is not optimal. Numerische Mathematik, 13(4), 1969. Springer.
30. D. Tam, R. Azimi, and M. Stumm. Thread clustering: Sharing-aware scheduling on SMP-CMP-SMT multiprocessors. In ACM EuroSys, 2007.