Effect of floating-gate polysilicon depletion on the erase efficiency of NAND flash memories

IEEE Electron Device Letters

Volumn 31, Issue 7, 2010, Pages 647-649

  Spessot, Alessio ^a   Monzio Compagnoni, Christian ^b,c   Farina, Fabrizio ^b,c   Calderoni, Alessandro ^a   Spinelli, Alessandro S ^b,c,d   Fantini, Paolo ^a  

^a R and D Technology Development   (Italy)

^b POLITECNICO DI MILANO   (Italy)

^c Italian University Nano Electronics Team IUNET   (Italy)

^d IFN CNR   (Italy)

Author keywords

Erase efficiency; Flash memories; Fowler Nordheim tunneling; semiconductor device modeling

Indexed keywords

DECA-NANOMETER; ERASE EFFICIENCY; EXPERIMENTAL EVIDENCE; EXPERIMENTAL INVESTIGATIONS; FLOATING-GATES; FOWLER-NORDHEIM TUNNELING; HIGHER TEMPERATURES; NAND FLASH MEMORY; POLYSILICON DEPLETION; SEMICONDUCTOR DEVICE MODELING; SHORT PULSE; TUNNEL OXIDE]; TUNNELING CURRENT;

DROPS; ELECTRIC FIELDS; NAND CIRCUITS; POLYSILICON;

FLASH MEMORY;

EID: 77954142598     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2048194     Document Type: Article

References (5)

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