Improvement of memory performance by high temperature annealing of the Al2 O3 blocking layer in a charge-trap type flash memory device

Applied Physics Letters

Volumn 96, Issue 22, 2010, Pages

  Park, Jong Kyung ^a   Park, Youngmin ^a   Lim, Sung Kyu ^b   Oh, Jae Sub ^b   Joo, Moon Sig ^c   Hong, Kwon ^c   Cho, Byung Jin ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b National Nano Fab Center (NNFC)   (South Korea)

^c Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BAND GAPS; BLOCKING LAYERS; CHARGE RETENTION; CHARGE TRAP; ENERGY LEVEL; EXPERIMENTAL EVIDENCE; FLASH MEMORY DEVICES; HIGH TEMPERATURE; HIGH-TEMPERATURE ANNEALING; MEMORY DEVICE; MEMORY PERFORMANCE; OPERATION SPEED; POST DEPOSITION ANNEALING; PROGRAM/ERASE; RETENTION PROPERTIES; TRAP DENSITY; TRAPPING EFFICIENCIES; TRAPPING LAYERS; UNDERLYING MECHANISM;

ALUMINUM; ANNEALING;

FLASH MEMORY;

EID: 77953555454     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3442502     Document Type: Article

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