Parasitic capacitances in double gate MOSFET

ITC 2010 - 2010 International Conference on Recent Trends in Information, Telecommunication, and Computing

Volumn , Issue , 2010, Pages 305-307

  Srivastava, Viranjay M ^a   Priyank, ^a   Singh, Sharad P ^a   Singh, G ^a  

^a JAYPEE UNIVERSITY OF INFORMATION TECHNOLOGY   (India)

Author keywords

Double gate mosfet; Interconnects; Parasitic capacitances; VLSI

Indexed keywords

CAPACITIVE LOADS; CLASSICAL APPROACH; DELAY MODELS; DOUBLE GATE MOSFET; DYNAMIC BEHAVIOURS; GATE DELAYS; INTRINSIC DELAY; MASK LAYOUT; MOS-FET; PARASITIC CAPACITANCE; PARASITIC COMPONENTS; PHYSICAL STRUCTURES; SWITCHING SPEED;

CAPACITANCE; LOGIC GATES; MOSFET DEVICES;

ELECTRON BEAM LITHOGRAPHY;

EID: 77953117066     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITC.2010.24     Document Type: Conference Paper

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