A novel self-align double gate MOSFET with source/drain tie

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2009, Pages 799-802

  Lin, Po Hsieh ^a   Lin, Jyi Tsong ^a   Eng, Yi Chuen ^a   Chen, Hsuan Hsu ^a   Kuo, Chih Hao ^a   Sun, Chih Hung ^a   Chiu, Hsien Nan ^a   Chang, Tzu Feng ^a   Chuang, Nai Chuan ^a  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE GATE; DOUBLE GATE MOSFET; DRAIN-INDUCED BARRIER LOWERING; NOVEL DEVICE ARCHITECTURES; ON/OFF CURRENT RATIO; SELF-ALIGN; SIMULATION RESULT; SOURCE/DRAIN TIES; SUBTHRESHOLD SWING;

DRAIN CURRENT; INTEGRATED CIRCUITS; MOS DEVICES; MOSFET DEVICES; QUALITY ASSURANCE; SAFETY FACTOR;

FAILURE ANALYSIS;

EID: 71049157662     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPFA.2009.5232719     Document Type: Conference Paper

References (4)

1. The International Technology Roadmap for Semiconductors, http://public.itrs.net/.
2. T. Dao, P. Montgomery, E. Luckowski, J. John, 1. Norbert, S. Stewart, B-Y Nguyen, and J. Teplik., " Industry Trend: Planar Double Gate Technology, " in Integrated Circuit Design and Technology, 2006. ICICDT, 2006, pp. 1-2.
3. R.-H. Yan et al., "Scaling the Si MOSFET: From bulk to SOl to bulk, " IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704-1710, Ju1.1992.
4. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, "Scaling theory for double-gate SOl MOSFETs, " IEEE Trans. Electron Devices, vol. 40, no. 12, pp. 2326-2329, Dec. 1993.