Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 801-806

  Qazi, Masood ^a   Tikekar, Mehul ^a   Dolecek, Lara ^a   Shah, Devavrat ^a   Chandrakasan, Anantha ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE ESTIMATION; COMPLEX STRUCTURE; DEEP SUB-MICRON TECHNOLOGY; HIGH-DIMENSIONAL; IMPORTANCE SAMPLING; MODEL REDUCTION TECHNIQUES; MONTE CARLO APPROACH; PROCESS VARIATION; SINGLE CHAINS; SPEED-UPS; TIMING DELAY; TIMING VARIATIONS; YIELD ANALYSIS;

ESTIMATION; TIME MEASUREMENT; TIMING CIRCUITS;

SAMPLING;

EID: 77953105147     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. A. Singhee and R. A. Rutenbar, "Statistical blockade: A novel method for very fast monte carlo simulation of rare circuit events, and its application," in DATE, 2007.
2. L. Dolecek, M. Qazi, D. Shah, and A. Chandrakasan, "Breaking the simulation barrier: Sram evaluation through norm minimization," in ICCAD, 2008.
3. M. H. Abu-Rahma et al., "A methodology for statistical estimation of read access yield in srams," in DAC, 2008.
4. R. Aitken and S. Idgunji, "Worst-case design and margin for embedded sram," in DATE, 2007.
5. D. P. Bertsekas and J. N. Tsitsiklis, Introduction to Probability. Athena Scientific, 2002.
6. J. Bucklew, Introduction to Rare Event Simulation. Springer, 2004.
7. A. Dembo and O. Zeitouni, Large Deviations Techniques and Applications. Springer, 1998.
8. X. Du and W. Chen, "Towards a better understanding of modeling feasibility robustness in engineering design," ASME Journal of Mechanical Design, 2000.
9. M. Tichy, Applied Methods of Structural Reliability. Boston: Kluwer Academic Publishers, 1993.
10. J. E. Stine et al., "Freepdk: An open-source variation-aware design kit," in ICMSE, 2007.
11. W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45 nm early design exploration," IEEE Trans. on Electron Devices, vol. 53, no. 11, pp. 2816-2823, 2006.
12. K. J. Kuhn, "Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale cmos," in IEDM, 2007.
13. K. J. Antreich and H. E. Graeb, "Circuit optimization driven by worst-case distances," in ICCAD, 1991.