Worst-case design and margin for embedded SRAM

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1289-1294

  Aitken, Robert ^a   Idgunji, Sachin ^a  

^a ARM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; EMBEDDED SYSTEMS; STATISTICAL METHODS; VALUE ENGINEERING;

DEVICE VARIABILITY; VALUE THEORY;

STATIC RANDOM ACCESS STORAGE;

EID: 34548318982     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364475     Document Type: Conference Paper

References (6)

1. B. Agrawal, F. Liu & S. Nassif, "Circuit Optimization Using Scale Based Sensitivities", Proc Custom Int. Circ. Conf, pp. 635-638, 2006.
2. S. Mukhopadhyay, H. Mahmoodi, & K. Roy, "Statistical design and optimization of SRAM cell for yield enhancement", Proc. ICCAD, pp. 10-13, 2004.
3. R.N.. Kanj, R.V. Joshi, S.R. Nassif, "Mixture Importance Sampling and Its Application to the Analysis of SRAM Designs in the Presence of Rare Failure Events", Proc. Design Aut. Conf, 5-3, 2006.
4. E.J. Gumbel, Les valeurs extrêmes des distri-butions statistiques, Ann. Inst. H. Poincaré, Vol 5, 115-158, 1935. (available online at numdam.org)
5. E. Castillo, Extreme Value Theory in Engineering, Academic Press, 1988.
6. D-M Kwai et al, "Detection of SRAM Cell Stability by Lowering Array Supply Voltage", Proc. Asian Test Symp., pp. 268-271, 2000