SimTag: Exploiting tag bits similarity to improve the reliability of the data caches

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 941-944

  Kim, Jesung ^a   Kim, Soontae ^a   Lee, Yebin ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DATA CACHES; ERROR PROTECTION; MAIN MEMORY; SMALL AREA; TRANSIENT ERRORS;

CACHE MEMORY;

EID: 77953091625     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Z. Herczeg, Ákos Kiss, D. Schmidt, N. Wehn, and T. Gyimóthy. Energy simulation of embedded XScale system with XEEMU. Journal of Embedded Computing, 3(3), 2009.
2. S. Kim and A. Somani, "Area efficient architectures for information integrity in cache memories," In Proc. ISCA, pp. 246-255, 1999.
3. S. Kim, "Reducing Area Overhead for Error-Protecting Large L2/L3 Caches," IEEE Trans. on Computers, Vol. 58, no. 3, pp. 300-310, March 2009.
4. W. Zhang, S. Gurumurthi, M. Kandemir, and A. Sivasubramaniam,"ICR: In-cache replication for enhancing data cache reliability," In Proc. Int. Conf. Depend. Syst. Netw., pp. 291-300, 2003.
5. C. Slayman, "Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations," IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 397-404, May 2005.
6. H. Asadi et al., "Vulnerability analysis of L2 cache elements to single event upsets," In Proc. Design, Automation and Test in Europe, pp. 1-6, Mar. 2006.
7. Austin, T. M., "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design," In Proc. MICRO, 1999.
8. M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown. "MiBench: A Free, Commercially Representative Embedded Benchmark Suite." In Proc. WWC-4, Dec. 2001.
9. S. Hong, S. Kim, "TEPS: Transient Error Protection Utilizing Sub-word Parallelism," In Proc. IEEE Computer Society Anal. Symp. on VLSI, pp.286-291, 2009.
10. L.D. Hung, M. Goshima, and S.Sakai, "Mitigating soft errors in highly associative cache with CAM-based tag," In Proc. IEEE Int.Conf. On Compoter Design 2005, pp.342-347, 2005.
11. K. Bhattacharya, N. Ranganathan, and S. Kim, "A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy," IEEE Trans. VLSI., Vol. 17, issue. 2, pp. 196-206, 2009.