Magnetic random accessible memory based magnetic content addressable memory cell design

IEEE Transactions on Magnetics

Volumn 46, Issue 6, 2010, Pages 1967-1970

  Wang, Weizhong ^a  

^a University of Wisconsin Milwaukee   (United States)

Author keywords

Associative memories; Magnetic device; Magnetic memories; Memory array

Indexed keywords

ASSOCIATIVE PROCESSING; ASSOCIATIVE STORAGE; CELLS; CYTOLOGY; MAGNETIC DEVICES; MAGNETIC STORAGE; MAGNETISM; MAGNETS;

ASSOCIATIVE MEMORY; CELL ARCHITECTURES; CELL DESIGN; CIRCUIT CONNECTIONS; DEVICE FABRICATIONS; MAGNETIC MEMORY; MAGNETIC TUNNELING JUNCTIONS; MEMORY ARRAY;

MEMORY ARCHITECTURE;

EID: 77952871401     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2010.2044981     Document Type: Article

References (8)

1. V. Ravikumar, R. Mahapatra, and L. Bhuyan, "EaseCAM: An energy and storage efficient TCAM-based router architecture for IP lookup," IEEE Trans. Comput., vol.54, pp. 521-533, May 2005.
2. T. Ikenaga and T. Ogura, "A fully parallel 1-MbCAMLSI for real-time pixel-parallel image processing," IEEE J. Solid State Circuits, vol.35, pp. 536-544, Apr. 2000.
3. A. Efthymiou and J. Garside, "A CAM with mixed serial-parallel comparison for use in low energy caches," IEEE Trans. VLSI Syst., vol.12, pp. 325-329, Mar. 2004.
4. S. Liu, F. Wu, and J. Kuo, "A novel low-voltage content- addressablememory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques," IEEE J. Solid-State Circuits, vol.36, pp. 712-716, Apr. 2001.
5. W.Wang and Z. Jiang, "Magnetic content addressable memory," IEEE Trans. Magn., vol.43, no.6, pp. 2355-2357, Jun. 2007.
6. W. Wang and Z. Jiang, "A planar magnetic content addressable memory cell," IEEE Trans. Magn., vol.44, no.11, pt. 1, pp. 2475-2478, Nov. 2008.
7. W. Wang and Z. Jiang, "Spin torque based magnetic content addressable memory," J. Appl. Phys., vol.105, no.7, pp. 07D121-07D121-3, Apr. 2009.
8. Z. Jiang and W. Wang, "A magnetic content addressable memory design with a single set of programming wires," IEEE Trans. Magn., vol.45, no.10, pp. 3788-3791, Oct. 2009.