Backgate bias and stress level impact on giant piezoresistance effect in thin silicon films and nanowires

Proceedings of the IEEE International Conference on Micro Electro Mechanical Systems (MEMS)

Volumn , Issue , 2010, Pages 464-467

  Passi, Vikram ^a   Ravaux, Florent ^b   Dubois, Emmanuel ^b   Raskin, Jean Pierre ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b Institut d'Electronique de Microélectronique et de Nanotechnologie   (France)

Author keywords

[No Author keywords available]

Indexed keywords

4-POINT BENDING; BACK-GATE BIAS; ELECTRICAL CHARACTERIZATION; HIGH STRESS; NONLINEAR CHARACTERISTICS; P-TYPE SILICON; PIEZORESISTANCE; PIEZORESISTANCE COEFFICIENTS; PIEZORESISTANCE EFFECTS; STRESS LEVELS; THIN SILICON FILMS; TOP-DOWN FABRICATION;

FIXTURES (TOOLING); MECHANICAL ENGINEERING; MECHANICS; NANOWIRES; REACTIVE ION ETCHING;

ELECTRIC WIRE;

EID: 77952778307     PISSN: 10846999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMSYS.2010.5442464     Document Type: Conference Paper

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