Pipelined hash-join on multithreaded architectures

Proceedings of the 3rd International Workshop on Data Management on New Hardware, DaMoN '07

Volumn , Issue , 2007, Pages

  Garcia, Philip ^a   Korth, Henry F ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b LEHIGH UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATABASE QUERY PROCESSING; JOIN OPERATION; MANAGEMENT SCHEME; MULTI CORE; MULTI-CORE PROCESSOR; MULTI-THREADING; MULTITHREADED; MULTITHREADED ARCHITECTURE; MULTITHREADED PROCESSORS; OPTIMAL NUMBER; PERFORMANCE GAIN;

MICROPROCESSOR CHIPS; MULTITASKING;

PIPELINE PROCESSING SYSTEMS;

EID: 77952413470     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1363189.1363191     Document Type: Conference Paper

References (24)

1. Intel multi-core processor architecture development backgrounder. Intel White Paper, 2005.
2. Multi-core processors-the next evolution in computing. AMD White Paper, 2005.
3. ® technology. Sun Microsystems White Paper, November 2005.
4. A. Ailamaki, D. J. DeWitt, M. D. Hill, and D. A. Wood. DBMSs on a modern processor: Where does time go? In Proc. 25th Int'l Conf. on Very Large Data Bases, pages 266-277, 1999.
5. D. Burger and J. R. Goodman. Billion-transistor architectures: There and back again. IEEE Computer, 37:22-28, Mar. 2004.
6. D. Carmean. Data management challenges on new computer architectures. In First Int'l Workshop on Data Management on New Hardware (DaMoN), June 2005. Oral Presentation.
7. S. Chen, A. Ailamaki, P. B. Gibbons, and T. C. Mowry. Improving hash join performance through prefetching. In Proc. Int'l Conf. on Data Engineering, 2004.
8. S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, R. L. Stamm, and D. M. Tullsen. Simultaneous multithreading: A platform for next-generation processors. IEEE Micro, 17 (5):12-18, September 1997.
9. P. Garcia and H. F. Korth. Hash-join algorithms on modern multithreaded computer architectures. In ACM Int'l Conf. on Computing Frontiers, May 2006.
10. P. C. Garcia. Optimizing database algorithms for modern computer architectures. Master's thesis, August 2005. http://www.cse.lehigh.edu/ ˜pcg2/thesispdf.
11. N. K. Govindaraju, J. Gray, R. Kumar, and D. Manocha. GPUTeraSort: High performance graphics co-processor sorting for large database management. In Proc. ACM SIGMOD Int'l Conf. on the Management of Data, June 2006.
12. G. Graefe. Encapsulation of parallelism in the volcano query processing system. In Proceedings of the 1990 ACM SIGMOD International Conference on Management of Data, pages 102-111, 1990.
13. W. D. Hillis and J. Guy L. Steele. Data parallel algorithms. Commun. ACM, 29 (12):1170-1183, 1986.
14. R. Kalla, B. Sinharoy, and J. M. Tendler. IBM Power5 chip: A dual-core multithreaded processor. 2004.
15. M. Kitsuregawa, H. Tanaka, and T. Moto-Oka. Application of hash to data base machine and its architecture. In 1New Generation Computing, volume 1, pages 63-74, 1983.
16. D. T. Marr, F. Binns, D. L. Hill, G. Hinton, D. A. Koufaty, J. A. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, (Q1): 4-15, 2002.
17. F. Mueller. Pthreads library interface, 1993.
18. S. Oks. Be aware: To hyper or not to hyper. Slava Oks Weblog http://blogs.msdn.com/slavao/archive/-2005/11/12/492119.aspx, Nov. 2005.
19. P. S. Otellini. Multi-core enables performance without power penalties. In Intel Developer Forum Keynote, http://www.embedded-controleurope.com/pdf/- ecedec05p26pdf, 2005.
20. A. Shatdal, C. Kant, and J. Naughton. Cache conscious algorithms for relational query processing. In Proceedings of 20th Int'l Conf. on Very Lage Data Bases, pages 510-524, 1994.
21. D. Towner and D. May. The 'uniform heterogeneous multi-threaded' processor architecture. In A. Chalmers, M. Mirmehdi, and H. Muller, editors, Communicating Process Architectures - 2001, pages 103-116. IOS Press, September 2001.
22. D. M. Tullsen, S. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In Proc. ACM IEEE Int'l Symposium on Computer Architecture, pages 191-202, 1996.
23. D. M. Tullsen, S. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In Proceedings of the 22nd Annual Int'l Symposium on Computer Architecture, June 1995.
24. J. Zhou, J. Cieslewicz, K. A. Ross, and M. Shah. Improving database performance on simultaneous multithreading processors. In VLDB '05: Proceedings of the 31st Int'l Conf. on Very Large Data Bases, pages 49-60, 2005.