Study of sub-30nm Thin Film Transistor (TFT) Charge-Trapping (CT) devices for 3D NAND flash application

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Hsu, Tzu Hsuan ^a   Lue, Hang Ting ^a   Hsieh, Chih Chang ^a   Lai, Erh Kun ^a   Lu, Chi Pin ^a,b   Hong, Shih Ping ^a,b   Wu, Ming Tsung ^a,b   Hsu, F H ^a,b   Lien, N Z ^a,b   Hsieh, Jung Yu ^a,b   Yang, Ling Wu ^a,b   Yang, Tahone ^a,b   Chen, Kuang Chao ^a,b   Hsieh, Kuang Yeu ^a   Liu, Rich ^a   Lu, Chih Yuan ^a  

^a Macronix International Co Ltd   (South Africa)

^b Technology Development Center   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BULK DEVICES; DC CHARACTERISTICS; JUNCTION LEAKAGES; MEMORY WINDOW; NAND FLASH; PLANAR DEVICES; RANDOM TELEGRAPH NOISE; READ CURRENT; SCALE DOWN; SUBTHRESHOLD SLOPE; TRI-GATE STRUCTURES;

ELECTRIC FIELDS; ELECTRON DEVICES; GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; TELEGRAPH;

THIN FILM TRANSISTORS;

EID: 77952344742     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424262     Document Type: Conference Paper

References (8)

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