Optimization of metallization processes for 32-nm-node highly reliable ultralow-k (k=2.4)/Cu Multilevel Interconnects incorporating a bilayer low-k barrier cap (k=3.9)

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Iguchi, M ^a   Yokogawa, S ^a   Aizawa, H ^a   Kakuhara, Y ^a   Tsuchiya, H ^a   Okada, N ^a   Imai, K ^a   Tohara, M ^a   Fujii, K ^a   Watanabe, T ^a,b  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BI-LAYER; HIGH TEMPERATURE; METALLIZATION PROCESS; MULTI LEVEL INTERCONNECTS; STRESS-INDUCED VOIDING; ULTRALOW-K;

AGRICULTURE;

ELECTRON DEVICES;

EID: 77952339449     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424270     Document Type: Conference Paper

References (4)

1. C.-K. Hu, L. Gignac, B.Baker, E. Liniger, R. Yu, and P. Flaitz, "Impact of Cu Microstructure on Electromigration Reliability", Proceedings of 2007 International Interconnect Technology Conference, pp.93-95 (2007).
2. S. Yokogawa, K. Kikuta, H. Tsuchiya, T. Takewaki, M. Suzuki, H. Toyoshima, Y. Kakuhara, N. Kawahara, T. Usami, K. Ohto, K. Fujii, Y. Tsuchiya, K. Arita, K. Motoyama, M. Tohara, T. Taiji, T. Kurokawa, and M. Sekine; "Trade-Off Characteristics Between Resistivity and Reliability for Scaled-Down Cu-Based Interconnects", IEEE Transactions on Electron Devices, Vol.55, pp.350-357 (2008).
3. N. Okada, Y. Matsubara, H. Kimura, H. Aizawa, and N. Nakamura, "Thermal stress of 140 nm-width Cu damascene interconnects", Interconnect Technology Conference, 2001. Proceedings of the IEEE 2002 International, pp.136-138 (2002).
4. M. Tagami, T. Fukase, A. Matsumoto, M. Iguchi, Y. Hayashi, and Y. Matsubara, "A new failure observation in 0.10-μm-wide Cu lines using optical beam induced resistance changes (OBIRCH)", Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International, pp.95-97 (2001).