Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors

Proceedings of the International Conference on Parallel Processing

Volumn 1, Issue , 1993, Pages 56-63

  Dahlgren, Fredrik ^b   Dubois, Michel ^b   Stenstrom, Per ^a  

^a LUND UNIVERSITY   (Sweden)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPROCESSING SYSTEMS; PROGRAM COMPILERS;

ADAPTIVE SCHEME; DATA PRE-FETCHING; DYNAMIC MEASURES; OVERALL EXECUTION; PREFETCHING TECHNIQUES; PROCESSOR UTILIZATION; SHARED MEMORY MULTIPROCESSOR; SOFTWARE AND HARDWARES;

MEMORY ARCHITECTURE;

EID: 84965078406     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.1993.92     Document Type: Conference Paper

References (15)

1. Boyle, J. et al. "Portable Programs for Parallel Processors". Holt, Rinehart, and Winston Inc. 1987.
2. Brorsson, M., Dahlgren, R, Nilsson, H., and Stenstrom, P. "The CacheMire Test Bench - A Flexible and Effective Approach for Simulation of Multiprocessors", In Proceedings of the 26th Annual Simulation Symposium, 1993.
3. Censier, L.M., and Feautrier, P. "A New Solution to Coherence Problems in Multicache Systems", In IEEE Transactions on Computers, 27(12), pp. 1112-1118, December 1978.
4. Dahlgren, F., Dubois, M., and Stenstrom, P. "Sequential Prefetching Schemes for Shared Memory Multiprocessors". Technical Report, Department of Computer Engineering, Lund University, Sweden.
5. Dubois, M. et al, "The Detection and Elimination of Useless Misses in Multiprocessors", In Proc of the 20th Int Symposium on Computer Architecture, May 1993.
6. Fu, J. and Patel, J.H."Data Prefetching in Multiprocessor Vector Cache Memories". In Proc of the 18th Int Symposium on Computer Architecture, pp.54-63, May 1991.
7. Gharachorloo, K., Gupta, A., Hennessy, J. "Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors", in Proc ofASPLOS IV, pp.245-257, 1991.
8. Gupta, A. and Weber, W.-D. "Cache Invalidation Patterns in Shared-Memory Multiprocessors", In IEEE Transactions on Computers, Vol. 41, No.7, pp. 794-810, 1992.
9. Hagersten, E. "Toward Scalable Cache Only Memory Architectures". PhD thesis, Swedish Institute of Computer Science, Oct. 1992 (SICS Dissertation Series 08)
10. Lee R., Yew P-C, and Lawrie D. "Data Prefetching in Shared-Memory Multiprocessors", In Proc 1987 Int Conf on Parallel Processing, pp.28-31, 1987.
11. Lenoski, D.E. et al, "The Stanford DASH Multiprocessor", In IEEE Computer, pp.63-79, March 1992.
12. Mowry, T. and Gupta, A. "Tolerating Latency through Software-Controlled Prefetching in Scalable Shared-Memory Multiprocessors", In Journal of Parallel and Distributed Computing, 1991.
13. Singh, J.P., Weber, W.-D., and Gupta, A. "SPLASH: Stanford Parallel Applications for Shared-Memory", In Computer Architecture News, 20(1):544, March 1992.
14. Smith, AJ. "Sequential Program Prefetching in Memory Hierarchies", In IEEE Computer, Vol. 11, No. 12, pp.7-21, Dec. 1978.
15. Stenstrom, P. "A Survey of Cache Coherence Scheme for Multiprocessors", In IEEE Computer, Vol. 23, No. 6, pp. 12-24, June 1990.