Improving pipelined soft processors with multithreading

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2007, Pages 210-215

  Labrecque, Martin ^a   Steffan, J Gregory ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

AREA EFFICIENCIES; AREA EFFICIENT; CLOCK FREQUENCIES; MULTITHREADED; MULTITHREADING; NUMBER OF THREADS; PROGRAMMABLE LOGICS; SINGLE THREADED; SOFT PROCESSORS;

COMPUTER ARCHITECTURE; DESIGN; MULTITASKING;

PIPELINE PROCESSING SYSTEMS;

EID: 48149101627     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380649     Document Type: Conference Paper

References (11)

1. B. Fort, D. Capalija, Z. G. Vranesic, and S. D. Brown, "A multithreaded soft processor for SoPC area reduction," in Proc. of FCCM '06. Washington, DC, USA: IEEE Computer Society, 2006, pp. 131-142.
2. R. Dimond, O. Mencer, and W. Luk, "Applicationspeci customisation of multi-threaded soft processors," IEE Proceedings-Computers and Digital Techniques, vol. 153, no. 3, pp. 173-180, May 2006.
3. P. Yiannacouras, J. G. Steffan, and J. Rose, "Exploration and customization of FPGA-based soft processors," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, February 2007.
4. Altera Corporation, "Quartus II," San Jose, CA, USA, Altera.
5. Mentor Graphics Corp., "Modelsim SE," http://www.model.com, Mentor Graphics, 2004.
6. J. Veenstra and R. Fowler, "MINT: a front end for efficient simulation of shared-memory multiprocessors," in Proc. of MASCOTS '94, NC, USA, January 1994, pp. 201-207.
7. S. A. Przybylski, T. R. Gross, J. L. Hennessy, N. P. Jouppi, and C. Rowen, "Organization and VLSI implementation of MIPS," Stanford University, CA, USA, Tech. Rep., 1984.
8. M. G. et al., "MiBench: A free, commercially representative embedded benchmark suite," in Proc. of WWC '01, December 2001.
9. F. Campi, R. Canegallo, and R. Guerrieri, "IP-reusable 32-bit VLIW RISC core," in Proc. of the 27th European Solid-State Circuits Conf, 2001, pp. 456-459.
10. L. Shannon and P. Chow, "Standardizing the performance assessment of reconfigurable processor architectures," in Proc. of FCCM '03, 2003, pp. 282-283.
11. M. Labrecque, P. Yiannacouras, and J. G. Steffan, "Custom code generation for soft processors," in Proc. of RAAW '06, Florida, US, December 2006.