High-throughput Bayesian computing machine with reconfigurable hardware

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2010, Pages 73-82

  Lin, Mingjie ^a   Lebedev, Ilia ^a   Wawrzynek, John ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Bayesian computing; Reconfigurable hardware

Indexed keywords

BAYESIAN; BAYESIAN COMPUTING; BAYESIAN PROBLEM; CODE COMPILATION; COMPUTING MACHINES; DIGITAL COMMUNICATIONS; DIRECTED ACYCLIC GRAPHS; DISTRIBUTED MEMORY; FLOATING POINT OPERATIONS; HARDWARE DESIGN; HARDWARE STRUCTURES; HIGH THROUGHPUT; INTEL PROCESSORS; MAXIMAL MATCHINGS; MEMORY ALLOCATION; NETWORK EVALUATION; NEW APPLICATIONS; PROBABILISTIC NETWORK; PROCESSING NODES; TASK GRAPH;

ARTIFICIAL INTELLIGENCE; BAYESIAN NETWORKS; CARRY LOGIC; COMPUTERS; DIGITAL COMMUNICATION SYSTEMS; DISTRIBUTED PARAMETER CONTROL SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; LOGIC DESIGN; LOGIC GATES; PIPELINE PROCESSING SYSTEMS; REUSABILITY; SIGNAL PROCESSING; THROUGHPUT;

RECONFIGURABLE HARDWARE;

EID: 77951575084     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1723112.1723127     Document Type: Conference Paper

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