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Volumn 5992 LNCS, Issue , 2010, Pages 157-168

A fused hybrid floating-point and fixed-point dot-product for FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING BLOCKES; CLOCK FREQUENCY; CONFIGURABLE; DATA-PATHS; HYBRID FLOATING-POINT; INTERNAL REPRESENTATION; POINT NUMBERS; SCIENTIFIC COMPUTING; SPEED-UPS; WORD LENGTH; XILINX FPGA;

EID: 77951281956     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-12133-3_16     Document Type: Conference Paper
Times cited : (20)

References (10)
  • 5
    • 51849153301 scopus 로고    scopus 로고
    • High Throughput FPGA-based Floating Point Conjugate Gradient Implementation
    • Roldao, A., Constantinides, G.: High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. In: Proc. of Applied Reconfigurable Computing, pp. 75-86 (2008)
    • (2008) Proc. of Applied Reconfigurable Computing , pp. 75-86
    • Roldao, A.1    Constantinides, G.2
  • 7
    • 34648814129 scopus 로고    scopus 로고
    • High-performance reduction circuits using deeply pipelined operators on FPGAs
    • DOI 10.1109/TPDS.2007.1068
    • Zhuo, L., Morris, G., Prasanna, V.: High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. IEEE Transactions on Parallel and Distributed Systems 18, 1377-1392 (2007) (Pubitemid 47456003)
    • (2007) IEEE Transactions on Parallel and Distributed Systems , vol.18 , Issue.10 , pp. 1377-1392
    • Zhou, L.1    Morris, G.R.2    Prasanna, V.K.3
  • 10
    • 77951291527 scopus 로고    scopus 로고
    • Collaborative Project, accessed on 02/01/2009
    • Collaborative Project, Multi-precision Floating Point Library, http://www.mpfr.org/ (accessed on 02/01/2009)
    • Multi-precision Floating Point Library


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.