Design and test strategies for microarchitectural post-fabrication tuning

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2009, Pages 84-90

  Liang, Xiaoyao ^a   Lee, Benjamin C ^b   Wei, Gu Yeon ^c   Brooks, David ^c  

^a SUZHOU UNIVERSITY   (China)

^b STANFORD UNIVERSITY   (United States)

^c HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP PERFORMANCE; CRITICAL DELAYS; ENERGY EFFICIENT; FABRICATED CHIPS; INTEGRATED FRAMEWORKS; MICRO ARCHITECTURES; ON CHIPS; POST-FABRICATION; POWER DISTRIBUTIONS; PROCESS VARIATION; RANDOM VARIATION; REGRESSION MODEL; STATISTICAL ANALYSIS; SYSTEMATIC VARIATION; TECHNOLOGY SCALING; TEST STRATEGIES; TESTING FRAMEWORK; TESTING TIME;

DESIGN; INTEGRATED CIRCUIT MANUFACTURE; REGRESSION ANALYSIS; TUNING;

FABRICATION;

EID: 77951014823     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413170     Document Type: Conference Paper

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