Thermal mitigation using thermal through silicon via (TTSV) in 3-D ICs

IMPACT Conference 2009 International 3D IC Conference - Proceedings

Volumn , Issue , 2009, Pages 182-185

  Singh, Shiv Govind ^a   Tan, Chuan Seng ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; CHIP TEMPERATURE; EXTENSION LENGTH; FINITE ELEMENT MODELING; ILD LAYERS; OXIDE LINERS; SI SUBSTRATES; THERMAL SIMULATIONS; THIN LAYERS; THROUGH-SILICON-VIA;

THREE DIMENSIONAL;

EID: 77950849517     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMPACT.2009.5382145     Document Type: Conference Paper

References (10)

1. K. Banerjee, S.J. Souri, P. Kapur, and K.C. Saraswat, "3-D ICs: A novel chip design for improving deep submicron interconnect performance and system on-chip integration," Proc. IEEE, Vol. 89, No. 5, May 2001, pp. 602-633.
2. A. Rahman and R. Reif, "System level performance evaluating of three dimensional integrated circuit," IEEE transaction on very Large Scale Integration (VLSI) system, Vol. 8, 2000, pp 671-678.
3. A. Rahman, A. Fan and R. Reif, "Comparison of key performance metrics in two and three dimensional integrated circuits," Proc. IITC, 2000, pp.18-20.
4. Im and K. Banerjee, "Full Chip Thermal Analysis of Planner (2-D) and vertically Integrated (3-D) High Performance ICs," Int. Electron Device Meeting, 2000, pp. 727-730.
5. A. Rahman and R. Reif, "Thermal analysis of three-dimensional (3-D) integrated circuits (ICs)," Proc. IITC, 2001, pp. 157-159.
6. S. Lee, T.F. Lemczyk, and M. M. Yovanovich, "Analysis of Thermal Vias in High Density Interconnect Technology," in 8th IEEE Semi-Therm Symposium, pp. 55-61, Feb. 1992.
7. T.-Y. Chiang, S. J. Souri, C. O. Chui, and K. C. Saraswat, "Thermal analysis of heterogeneous 3D ICs with various integration scenarios," Int. Electron Device Meeting, 2001, pp. 681-684.
8. B. Goplen and S. S. Sapatnekar, "Thermal Via Placement in 3D ICs," ISPD'05, April 3-6, 2005, San Francisco, California, USA.
9. R. Reif, C. S. Tan, A. Fan, K. N. Chen, S. Das, and N. Checka, "3-D Interconnects Using Cu Wafer Bonding : Technology and Applications," Adcanced Metallization Conference, 2002, pp. 37-45.
10. Alexander A. Balandin, Suchismita Ghosh, Wenzhong Bao, Irene Calizo, Desalegne Teweldebrhan, Feng Miao, Chun Ning Lau, "Superior Thermal Conductivity of Single-Layer Graphene," Nano Lett., 2008, 8 (3), pp 902-907.