Design of coarse-grained dynamically reconfigurable architecture for DSP applications

ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs

Volumn , Issue , 2009, Pages 338-343

  Zhang, Chenxin ^a   Lenart, Thomas ^a   Svensson, Henrik ^a   Öwall, Viktor ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

Coarse grained reconfigurable architecture; Dynamically reconfigurable cell array; FFT; Hybrid interconnect

Indexed keywords

CELL ARRAY; COARSE GRAINED RECONFIGURABLE ARCHITECTURE; COARSE-GRAINED; COMPILE TIME; DIGITAL SIGNALS; DSP APPLICATION; DYNAMIC RECONFIGURABILITY; DYNAMICALLY RECONFIGURABLE ARCHITECTURE; EXECUTION TIME; FFT PROCESSORS; INTERCONNECT NETWORKS; MEMORY ELEMENT; PERFORMANCE EVALUATION; PROCESSING CONDITION; PROPOSED ARCHITECTURES; RADIX 2; RE-CONFIGURABLE; RECONFIGURABILITY; RUNTIMES;

DESIGN; DIGITAL SIGNAL PROCESSORS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERCONNECTION NETWORKS; MAPPING; SIGNAL PROCESSING;

FAST FOURIER TRANSFORMS;

EID: 77950473150     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReConFig.2009.49     Document Type: Conference Paper

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