Architectures for dynamic data scaling in 2/4/8K pipeline FFT cores

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 11, 2006, Pages 1286-1290

  Lenart, Thomas ^a   Öwall, Viktor ^a  

^a LUND INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Block floating point (BFP); Convergent BFP (CBFP); Digital holography; Digital video broadcasting (DVB); Dynamic data scaling; Fast fourier transform (FFT); Hybrid floating point; Orthogonal frequency division multiplexing (OFDM)

Indexed keywords

DIGITAL SIGNAL PROCESSING; FAST FOURIER TRANSFORMS; HOLOGRAPHY; IMAGE CODING; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; TELEVISION BROADCASTING;

BLOCK FLOATING POINT (BFP); CONVERGENT BFP (CBFP); DIGITAL HOLOGRAPHY; DIGITAL VIDEO BROADCASTING (DVB); DYNAMIC DATA SCALING; HYBRID FLOATING POINT;

DATA COMMUNICATION SYSTEMS;

EID: 33845544964     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.886407     Document Type: Article

References (12)

1. T. Lenart and V. Öwall, "A 2048 complex point FFT processor using a novel data scaling approach," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2003, pp. 45-48.
2. M. Gustafsson et al., "High resolution digital transmission microscopy - a Fourier holography approach," Opt. Lasers Eng., vol. 41, no. 3, pp. 553-563, Mar. 2004.
3. Digital Video Broadcasting (DVB); Framing Structure, Channel Coding, and Modulation for Digital Terrestrial Television, ETSI EN 300 744 v 1.4.1, Euro. Telecommun. Standards Inst., Sophia-Antipolis, France, 2001.
4. J. W. Cooley and J. W. Tukey, "An algorithm for machine calculation of complex Fourier series," Math. Comput., vol. 19, pp. 297-301, Apr. 1965.
5. S. He and M. Torkelson, "Designing pipeline FFT processor for OFDM (de)modulation," in Proc. URSI Int. Symp. Signals, Syst. Electron., 1998, pp. 257-262.
6. K. Kalliojärvi and J. Astola, "Roundoff errors is block-floating point systems," IEEE Trans. Signal Process., vol. 44, no. 4, pp. 783-790, Apr. 1996.
7. E. Bidet, C. Joanblanq, and P. Senn, "A fast single-chip implementation of 8192 complex point FFT," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 300-305, Mar. 1995.
8. F. Kristensen, P. Nilsson, and A. Olsson, "Reduced transceiver-delay for OFDM systems," in Proc. Vehicular Technol. Conf., VTC, 2004, pp. 1242-1245.
9. C. Del Toso et al., "0.5- μm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1781-1792, Nov. 1998.
10. Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, "A dynamic scaling FFT processor for DVB-T applications," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2005-2013, Nov. 2004.
11. C.-C. Wang, J.-M. Huang, and H.-C. Cheng, "A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers," IEEE Trans. Consumer Electron., vol. 51, no. 1, pp. 28-32, Feb. 2005.
12. T. Lenart et al., "Accelerating signal processing algorithm in digital holography using an FPGA platform," in Proc. Int. Conf. FPT, 2003, pp. 387-390.