Characterization of CMOS defects using transient signal analysis

Proceedings - 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1998

Volumn 1998-December, Issue , 1998, Pages 93-101

  Plusquellio, J F ^a   Chiarulli, D M ^b   Levitan, S P ^c  

^a Baltimore County   (United States)

^b Learning Research and Development Ctr   (United States)

^c University of Pittsburgh   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEFECTS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; FREQUENCY DOMAIN ANALYSIS; SIGNAL ANALYSIS; VLSI CIRCUITS;

ANALYSIS TECHNIQUES; COUPLING CAPACITOR; COUPLING MECHANISM; HARDWARE EXPERIMENT; RELATIVE CONTRIBUTION; SIGNAL VARIATIONS; TIME AND FREQUENCY DOMAINS; TRANSIENT SIGNAL ANALYSIS;

TRANSIENT ANALYSIS;

EID: 77950456630     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1998.732155     Document Type: Conference Paper

References (12)

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