Ground bouncing noise aware sequential MTCMOS circuits with data retention capability

ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

Volumn , Issue , 2009, Pages 534-537

  Jiao, Hailong ^a   Kursun, Volkan ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; DATA RETENTION; DESIGN METRICS; LEAKAGE POWER CONSUMPTION; MTCMOS CIRCUITS;

CMOS INTEGRATED CIRCUITS;

INTEGRATED CIRCUITS;

EID: 77950445413     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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3. J. Kao and A. Chandrakasan, "MTCMOS Sequential Circuits," Proceedings of the IEEE European Solid-State Circuits Conference, pp. 317-320, September 2001.
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8. M. H. Chowdhury, J. Gjanci, and P. Khaled, "Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip," Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 437-440, April 2008.
9. S. Kim, S. V. Kosonocky, and D. R. Knebel, "Understanding and Minimizing Ground Bounce during Mode Transition of Power Gating Structures," Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, pp. 22-25, August 2003.
10. H. Jiao and V. Kursun, "Ground Bouncing Noise Suppression Techniques for MTCMOS Circuits," Proceedings of the IEEE Asia Symposium on Quality Electronic Design, pp. 64-70, July 2009.