Design consideration for vertical nonvolatile memory device regarding gate-induced barrier lowering (GIBL)

IEICE Transactions on Electronics

Volumn E92-C, Issue 5, 2009, Pages 620-626

  Cho, Seongjae ^a   Lee, Jung Hoon ^a   Lee, Gil Sung ^a   Lee, Jong Duk ^a   Shin, Hyungcheol ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

Author keywords

3 D nonvolatile memory; Channel potential barrier; Gate induced barrier lowering (GIBL); NAND flash memory array; Saturation current

Indexed keywords

MEMORY ARCHITECTURE; NAND CIRCUITS; NONVOLATILE STORAGE; SILICON;

BARRIER LOWERING; CHANNEL POTENTIAL; NAND FLASH MEMORY; NON-VOLATILE MEMORY; SATURATION CURRENT;

FLASH MEMORY;

EID: 77950408870     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1587/transele.E92.C.620     Document Type: Article

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