Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

IEEE Transactions on Nanotechnology

Volumn 5, Issue 3, 2006, Pages 180-184

  Cho, Seongjae ^b   Park, Il Han ^b   Kim, Tae Hun ^b   Sim, Jae Sung ^b,c   Song, Ki Whan ^b   Lee, Jong Duk ^a,b,d   Shin, Hyungcheol ^a,b,e   Park, Byung Gook ^a,b,f,g  

^a IEEE

^b Seoul National University   (South Korea)

^c SAMSUNG Electronics   (South Korea)

^d School of Electrical Engineering   (South Korea)

^e Institute of Electronics Engineers of Korea IEEK   (South Korea)

^f Seoul National University   (South Korea)

^g Research Department

Author keywords

Operating schemes; Read disturbance; Two bit floating gate type nonvolative memory (NVM) cell

Indexed keywords

FLOATING-GATE-TYPE DEVICE; OPERATING SCHEMES; READ DISTURBANCE; TWO-BIT FLOATING-GATE-TYPE NONVOLATIVE MEMORY (NVM) CELL;

COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DIELECTRIC MATERIALS; FLASH MEMORY; MOSFET DEVICES;

NONVOLATILE STORAGE;

EID: 33646740226     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2006.869943     Document Type: Conference Paper

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