Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Volumn , Issue , 2009, Pages 169-172

  Weis, Marcus ^a   Pfitzner, Andrzej ^b   Kasprowicz, Dominik ^b   Emling, Rainer ^a   Fischer, Thomas ^a   Henzler, Stephan ^a   Maly, Wojciech ^c   Schmitt Landsiedel, Doris ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-DIMENSIONAL; 3D MEMORY; 6T-SRAM; AREA REDUCTION; CELL STABILITY; DOUBLE GATE TRANSISTOR; MEMORY CELL; SRAM CELL; WRITE OPERATIONS;

FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE; THREE DIMENSIONAL;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 77950336032     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2009.5166288     Document Type: Conference Paper

References (12)

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11. http:www.immersionlab.nlpdf/ASML PatterningArt E.pdf (18.02.2009)
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