Adder circuits with transistors using independently controlled gates

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 449-452

  Weis, Marcus ^a   Pfitzner, Andrzej ^b   Kasprowicz, Dominik ^b   Emling, Rainer ^a   Maly, Wojciech ^c   Schmitt Landsiedel, Doris ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDER CIRCUIT; AREA REDUCTION; BUILDING BLOCKES; DOUBLE GATE TRANSISTOR; LOGIC DENSITY; PARALLEL PREFIX ADDER; POWER CONSUMPTION; TRANSISTOR COUNT;

ADDERS; TRANSISTORS;

DELAY CIRCUITS;

EID: 70350141754     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5117782     Document Type: Conference Paper

References (8)

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