Technology and design aspects of ultra-thin silicon chips for bendable electronics

2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Volumn , Issue , 2009, Pages 149-154

  Richter, Harald ^a   Rempp, Horst D ^a   Hassan, Mahadi Ul ^a   Harendt, Christine ^a   Wacker, Nicoleta ^a   Zimmermann, Martin ^a   Burghartz, Joachim N ^a  

^a Institut fur Mikroelektronik Stuttgart   (Germany)

Author keywords

CMOS integrated circuits; Electrochemical processes; Flexible structures; Piezoresistivity; Stress

Indexed keywords

3D CIRCUIT; BULK SILICON; CHIP SURFACES; CIRCUIT DESIGNS; CIRCUIT PERFORMANCE; CMOS CHIPS; CMOS GATE; CMOS PROCESSING; CMOS TRANSISTORS; CONTROL WAFERS; ELECTROCHEMICAL PROCESS; ELECTROCHEMICAL PROCESSES; EMERGING MARKETS; FOIL SYSTEM; FULLY OPERATIONAL; MECHANICAL STRESS; MIXED-SIGNAL CIRCUITS; MOS TRANSISTORS; PARAMETER VARIATION; PARAMETRIC YIELD; PIEZORESISTIVE EFFECTS; PIEZORESISTIVITY; PLASTIC ELECTRONICS; PROCESS PARAMETERS; SI CHIPS; STANDARD CMOS PROCESS; SYSTEM OF CHIPS; TECHNOLOGY-BASED; TEST CIRCUIT; ULTRA-THIN; ULTRA-THIN CHIPS; ULTRATHIN SILICON;

DESIGN; DIGITAL CIRCUITS; FLEXIBLE ELECTRONICS; FLEXIBLE STRUCTURES; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LUMPED PARAMETER NETWORKS; POLYIMIDES; SILICON WAFERS; STRESSES; TECHNOLOGY; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 77950315899     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2009.5166284     Document Type: Conference Paper

References (11)

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