Design technology of stacked NAND type 1-transistor FeRAM

IEEJ Transactions on Electronics, Information and Systems

Volumn 130, Issue 2, 2010, Pages 226-234

  Sugano, Koichi ^a   Watanabe, Shigeyoshi ^a  

^a SHONAN INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Feram; Ferro electric; Nand structure; Non volatile memory; Stacked structure; Universal memory

Indexed keywords

DESIGN;

ACCESS TIME; BIT LINES; CELL ARRAY; COLUMN DECODERS; CORE CIRCUIT; DELAY TIME; DESIGN RULES; DESIGN TECHNOLOGIES; FEASIBILITY STUDIES; MEMORY CELL ARRAYS; NAND STRUCTURES; NON-VOLATILE MEMORIES; STACKED STRUCTURE; WORDLINES;

RANDOM ACCESS STORAGE;

EID: 77949396470     PISSN: 03854221     EISSN: 13488155     Source Type: Journal    
DOI: 10.1541/ieejeiss.130.226     Document Type: Article

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