2.4F 2 memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM

IEEE Transactions on Electron Devices

Volumn 48, Issue 8, 2001, Pages 1599-1603

  Endoh, Tetsuo ^a,b   Suzuki, Masahiko ^b   Sakuraba, Hiroshi ^a,b   Masuoka, Fujio ^a,b  

^a IEEE   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

Cell design; DRAM; Stacked surrounding gate transistor (S SGT); Surrounding gate transistor (SGT)

Indexed keywords

CELL DESIGN; MEMORY CELL TECHNOLOGY;

COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; ELECTRODES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE;

GATES (TRANSISTOR);

EID: 0035423662     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.936567     Document Type: Article

References (8)

1. A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs
2. An experimental DRAM with a NAND-structured cell
3. The analysis of the stacked-surrounding gate transistor (S-SGT) DRAM for the high speed and low voltage operation
4. New three-dimensional memory array architecture for future ultrahigh-density DRAM
5. The stacked-SGT DRAM using 3D-building memory array technology
6. 2 memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM
7. 2 memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM
8. A novel circuit technology with surrounding gate transistors (SGTs) for ultra high density DRAMs