New three-dimensional memory array architecture for future ultrahigh-density DRAM

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 4, 1999, Pages 476-483

  Endoh, Tetsuo ^a   Shinmei, Katsuhisa ^a   Sakuraba, Hiroshi ^a   Masuoka, Fujio ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; GATES (TRANSISTOR);

THREE DIMENSIONAL MEMORY ARRAYS; ULTRAHIGH DENSITY DYNAMIC RANDOM ACCESS STORAGE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033115735     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.753680     Document Type: Article

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