Parallel genetic algorithm for VLSI standard cell placement

ACT 2009 - International Conference on Advances in Computing, Control and Telecommunication Technologies

Volumn , Issue , 2009, Pages 80-84

  Subbaraj, P ^a   Saravana Sankar, S ^a   Anand, S ^a  

^a KALASALINGAM UNIVERSITY   (India)

Author keywords

Genetic algorithm; Parallel computing; Placement; VLSI physical design

Indexed keywords

BENCH MARKS; COMPUTATIONAL TIME; PARALLEL COMPUTING; PARALLEL GA; PARALLEL GENETIC ALGORITHMS; PARALLEL TECHNIQUES; PLACEMENT; SOLUTION QUALITY; STANDARD-CELL PLACEMENT; VLSI PHYSICAL DESIGN; WIRE LENGTH;

ELECTRIC BATTERIES; GENETIC ALGORITHMS; PARALLEL ARCHITECTURES;

COMPUTATION THEORY;

EID: 77949294580     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACT.2009.30     Document Type: Conference Paper

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