FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm

Journal of Systems Architecture

Volumn 56, Issue 2-3, 2010, Pages 116-123

  Van Dyken, Jason ^a   Delgado Frias, José G ^a  

^a Washington State University   (United States)

Author keywords

Advanced Encryption Standard (AES); FPGA; Performance; Power

Indexed keywords

ADVANCED ENCRYPTION STANDARD; ADVANCED ENCRYPTION STANDARD ALGORITHMS; ENCRYPTION SCHEMES; LOW-POWER CONSUMPTION; POWER CONSUMPTION; SIGNAL POWER; ULTRA HIGH SPEED;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); STANDARDS;

CRYPTOGRAPHY;

EID: 77649274742     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2009.12.001     Document Type: Article

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