An efficient architecture for the AES mix columns operation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4637-4640

  Li, Hua ^a   Friggstad, Zac ^a  

^a UNIVERSITY OF LETHBRIDGE   (Canada)

Author keywords

AES; Cryptography; Galois field; Mix columns

Indexed keywords

AES; COMPACT ARCHITECTURE; EFFICIENT ARCHITECTURE; GALOIS FIELD; GATE COUNT; HARDWARE IMPLEMENTATIONS; MIX COLUMNS;

CRYPTOGRAPHY;

HARDWARE;

EID: 67649136129     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465666     Document Type: Conference Paper

References (4)

1. N. I. of Standards and Technology, Federal Information Processing Standard 197, The Advanced Encryption Standard (AES), http://csrc.nist.gov/ publications/fips/fips197/fips197.pdf, 2001.
2. H. Kuo, I. Verbauwhede, and P. Schaumont, "A 2.29 gbits/sec, 56 mw non-pipelined rijndael aes encryption ic in a 1.8v, 0.18 um cmos technology." [Online]. Available: citeseer.nj.nec.com/kuo02gbitssec.html
3. S. Mangard, M. Aigner, and S. Moninikus, "A highly regular and scalable aes hardware architecture," IEEE Transactions on Computers, vol. 52, no. 4, pp. 483-491, April 2003.
4. A. Rudra, P. Dubey, C. Jutla, V. Kumar, J. Rao, and P. Rohatgi, "Efficient rijndael encryption implementation with composite field arithmetic," in Proc. Workshop Cryptographic Hardware and Embedded Systems, ser. CHES, 2001, pp. 171-184.